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datasheet ics85408bgi revision b july 2, 2009 1 ?2009 integrated device technology, inc. low skew, 1-to-8, differential-to-lvds clock ICS85408I general description the ICS85408I is a low skew, high performance 1-to-8 differential-to-lvds clock distribution chip and a member of the hiperclocks? family of high performance clock solutions from idt. the ICS85408I clk, nclk pair can accept most differential input levels and translates them to 3.3v lvds output levels. utilizing low voltage differential signaling (lvds) , the ICS85408I provides a low power, low noise, low skew, point-to-point solution for distributing lvds clock signals. guaranteed output and part-to-part skew specifications make the ICS85408I ideal for those applications demanding well defined performance and repeatability. features ? eight differential lvds output pairs ? one differential clock input pair ? clk/nclk can accept the following differential input levels: lvpecl, lvds, lvhstl, hcsl, sstl ? maximum output frequency: 700mhz ? translates any differential inpu t signal (lvpecl, lvhstl, sstl, hcsl) to lvds levels without external bias networks ? translates any single-ended input signal to lvds with resistor bias on nclk input ? multiple output enable inputs for disabling unused outputs in reduced fanout applications ? additive phase jitter, rms: 167fs (typical) ? output skew: 50ps (maximum) ? part-to-part skew: 550ps (maximum) ? propagation delay: 2.4ns (maximum) ? 3.3v operating supply ? -40c to 85c ambient operating temperature ? available in both standard (rohs 5) and lead-free (rohs 6) packages hiperclocks? ic s 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 nq6 q6 nq5 q5 nq4 q4 nq3 q3 nq2 q2 nq1 q1 q7 nq7 gnd oe v dd v dd gnd v dd clk ncl k q0 nq0 clk nclk oe q0 nq0 q1 nq1 q2 nq2 q3 nq3 q4 nq4 q5 nq5 q6 nq6 q7 nq7 pin assignment ICS85408I 24-lead tssop 4.4mm x 7.8mm x 0.925mm package body g package top view block diagram
ICS85408I datasheet low skew, 1-to-8, differential-to-lvds clock distribution chip ics85408bgi revision b july 2, 2009 2 ?2009 integrated device technology, inc. table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics number name type description 1, 2 nq6, q6 output differential out put pair. lvds interface levels. 3, 4 nq5, q5 output differential out put pair. lvds interface levels. 5, 6 nq4, q4 output differential out put pair. lvds interface levels. 7, 8 nq3, q3 output differential out put pair. lvds interface levels. 9, 10 nq2, q2 output differential out put pair. lvds interface levels. 11, 12 nq1, q1 output differential out put pair. lvds interface levels. 13, 14 nq0, q0 output differential out put pair. lvds interface levels. 15 nclk input pullup inverting differential clock input. 16 clk input pulldown non-inverting differential clock input. 17, 19, 20 v dd power positive supply pins. 18, 21 gnd power power supply ground. 22 oe input pullup output enable. controls the enabling and di sabling of outputs qx, nqx. when high, the outputs are enabled. w hen low, the outputs are in high-impedance. lvcmos / lvttl interface levels. 23, 24 nq7, q7 output differential out put pair. lvds interface levels. symbol parameter test conditio ns minimum typical maximum units c in input capacitance 4pf c pd power dissipation capacitance (per output) 4pf r pullup input pullup resistor 51 k ? r pulldown input pulldown resistor 51 k ?
ICS85408I datasheet low skew, 1-to-8, differential-to-lvds clock distribution chip ics85408bgi revision b july 2, 2009 3 ?2009 integrated device technology, inc. function tables table 3a. output enable function table table 3b. clock input function table note 1: please refer to the application information section, wiring the differential input to accept single-ended levels. inputs outputs oe q[0:7], nq[0:7] 0 high-impedance 1 active (default) inputs outputs input to output mode polarity clk nclk q[0:7] nq[0:7] 0 1 low high differential to differential non-inverting 1 0 high low differential to differential non-inverting 0 biased; note 1 low high single-ended to differential non-inverting 1 biased; note 1 high low single-ended to differential non-inverting biased; note 1 0 high low single-ended to differential inverting biased; note 1 1 low high single-ended to differential inverting
ICS85408I datasheet low skew, 1-to-8, differential-to-lvds clock distribution chip ics85408bgi revision b july 2, 2009 4 ?2009 integrated device technology, inc. absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operati on of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. lvds power supply dc characteristics, v dd = 3.3v 5%, t a = -40c to 85c table 4b. lvcmos/lvttl dc characteristics, v dd = 3.3v 5%, t a = -40c to 85c table 4c. differential dc characteristics, v dd = 3.3v 5%, t a = -40c to 85c note 1: v il should not be less than -0.3v. note 2: common mode input voltage is defined as v ih . item rating supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, i o (lvds) continuos current surge current 10ma 15ma package thermal impedance, ja 70c/w (0 mps) storage temperature, t stg -65 c to 150 c symbol parameter test conditio ns minimum typical maximum units v dd positive supply voltage 3.135 3.3 3.465 v i dd power supply current 90 ma symbol parameter test conditions minimum typical maximum units v ih input high voltage 2 v dd + 0.3 v v il input low voltage -0.3 0.8 v i ih input high current v dd = v in = 3.465v 5 a i il input low current v dd = 3.465v, v in = 0v -150 a symbol parameter test conditio ns minimum typical maximum units i ih input high current clk v dd = v in = 3.465v 150 a nclk v dd = v in = 3.465v 5 i il input low current clk v dd = 3.465v, v in = 0v -5 a nclk v dd = 3.465v, v in = 0v -150 a v pp peak-to-peak voltage; note 1 0.15 1.3 v v cmr common mode input voltage; note 1, 2 gnd + 0.5 v dd ? 0.85 v
ICS85408I datasheet low skew, 1-to-8, differential-to-lvds clock distribution chip ics85408bgi revision b july 2, 2009 5 ?2009 integrated device technology, inc. table 4d. lvds dc characteristics, v dd = 3.3v 5%, t a = -40c to 85c table 5. ac characteristics, v dd = 3.3v 5%, t a = -40c to 85c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. note: all parameters measured at f max unless noted otherwise. note 1: measured from the differential input crossi ng point to the differential output crossing point. note 2: defined as skew between outputs at the same supply volt age and with equal load conditions. measured at the differential crossing point of the input to the differential output crossing point. note 3: defined as skew between outputs on different devices oper ating at the same supply voltages and with equal load conditio ns. using the same type of inputs on each device, the ou tputs are measured at the differential cross points. note 4: this parameter is defined in accordance with jedec standard 65. note 5: these parameters are guaranteed by characterization. not tested in production. symbol parameter test conditio ns minimum typical maximum units v od differential ou tput voltage r l = 100 ? 250 400 600 mv ? v od v od magnitude change r l = 100 ? 50 mv v os offset voltage r l = 100 ? 1.125 1.4 1.6 v ? v os v os magnitude change r l = 100 ? 50 mv i oz high impedance leakage -10 +10 a i off power off leakage -1 +1 a i osd differential output short circuit current -5.5 ma i os /i osb output short circuit current -12 ma symbol parameter test conditio ns minimum typical maximum units f max output frequency 700 mhz t pd propagation delay; note 1 1.6 2.4 ns t jit buffer additive phase jitter, rms; refer to additive phase jitter section 156.25mhz, integration range: (12khz ? 20mhz) 167 fs tsk (o) output skew; note 2, 4 50 ps tsk (pp) part-to-part skew; note 3, 4 550 ps t r / t f output rise/fall time 20% to 80% 50 600 ps odc output duty cycle 45 55 % t pzl, t pzh output enable time; note 5 5ns t plz, t phz output disable time; note 5 5ns
ICS85408I datasheet low skew, 1-to-8, differential-to-lvds clock distribution chip ics85408bgi revision b july 2, 2009 6 ?2009 integrated device technology, inc. additive phase jitter the spectral purity in a band at a specific offset fr om the fundamental compared to the power of t he fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the specified plot in many applications. phase noise is defined as the ratio of the noise power present in a 1hz band at a specified offset from the fundament al frequency to the power value of the fundamental. this ratio is expressed in decibels (dbm) or a ratio of the power in the 1hz band to the power in the fundamental. when the required offset is specif ied, the phase noise is called a dbc value, which simply means dbm at a specif ied offset from the fundamental. by investigating jitter in the frequency domain, we get a better understanding of its effect s on the desired application over the entire time record of the signal. it is mathematically possible to calculate an expected bit error rate given a phase noise plot. as with most timing specificat ions, phase noise measurements has issues relating to the limitations of the equipment. often the noise floor of the equipment is higher than the noise floor of the device. this is illustrated above. the device m eets the noise floor of what is shown, but can actually be lower. the phase noise is dependent on the input source and measurement equipment. ssb phase noise dbc/hz offset from carrier frequency (hz) additive phase jitter @156.25mhz 12khz ? 20mhz = 167fs (typical)
ICS85408I datasheet low skew, 1-to-8, differential-to-lvds clock distribution chip ics85408bgi revision b july 2, 2009 7 ?2009 integrated device technology, inc. parameter measureme nt information 3.3v lvds output load ac test circuit propagation delay output skew differential input level part-to-part skew output duty cycle/pulse width/period scope qx nqx lvds 3.3v5% power supply +? float gnd v dd t pd q[0:7] nq[0:7] nclk clk t sk(o) qx nqx qy nqy v dd nclk clk gnd v cmr cross points v pp t sk(pp) part 1 part 2 qx nqx qy nqy t pw t period t pw t period odc = x 100% q[0:7] nq[0:7]
ICS85408I datasheet low skew, 1-to-8, differential-to-lvds clock distribution chip ics85408bgi revision b july 2, 2009 8 ?2009 integrated device technology, inc. parameter measurement in formation, continued output rise/fall time differential output voltage setup differential output short circuit setup offset voltage setup power off leakage setup output short circuit current setup 20% 80% 80% 20% t r t f v od q[0:7] nq[0:7] ? ? ? 100 out out lvds dc input v od / ? v od v dd out out lvds dc input ? i osd v dd out out lvds dc input ? ? ? v os / ? v os v dd lvds ? i off v dd out lvds dc input ? i os ? i osb v dd out
ICS85408I datasheet low skew, 1-to-8, differential-to-lvds clock distribution chip ics85408bgi revision b july 2, 2009 9 ?2009 integrated device technology, inc. application information wiring the differential input to accept single-ended levels figure 1 shows how the differential input can be wired to accept single-ended levels. the reference voltage v_ref = v dd /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possibl e to the input pin. the ratio of r1 and r2 might need to be adjusted to position the v_ref in the center of the input voltage swing. fo r example, if the input clock swing is only 2.5v and v dd = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609. figure 1. single-ende d signal driving differential input recommendations for un used output pins outputs: lv d s o u t p u t s all unused lvds output pairs can be either left floating or terminated with 100 ? across. if they are left floating, there should be no trace attached. v_ref single ended clock input v dd clk nclk r1 1k c1 0.1u r2 1k
ICS85408I datasheet low skew, 1-to-8, differential-to-lvds clock distribution chip ics85408bgi revision b july 2, 2009 10 ?2009 integrated device technology, inc. differential clock input interface the clk /nclk accepts lvds, lvpecl, lvhstl, sstl, hcsl and other differential signals. bo th signals must meet the v pp and v cmr input requirements. figures 2a to 2f show interface examples for the hiperclocks clk/nclk input driven by the most common driver types. the input interfaces suggested here are examples only. please consult with the vendor of the driver component to confirm the driver termination requirements. for example, in figure 2a, the input termination applies for idt hiperclocks open emitter lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. 2a. hiperclocks clk/nclk input driven by an idt open emitter hiperclocks lvhstl driver figure 3c. hiperclocks clk/nclk input driven by a 3.3v lvpecl driver figure 2e. hiperclocks clk/nclk input driven by a 3.3v hcsl driver figure 2b. hiperclocks clk/nclk input driven by a 3.3v lvpecl driver figure 2d. hiperclocks clk/nclk input driven by a 3.3v lvds driver figure 2f. hiperclocks clk/nclk input driven by a 2.5v sstl driver r1 50 r2 50 1.8v zo = 50 ? zo = 50 ? clk nclk 3.3v lvhstl idt hiperclocks lvhstl driver hiperclocks input r3 125 r4 125 r1 84 r2 84 3.3v zo = 50 ? zo = 50 ? clk nclk 3.3v 3.3v lvpecl hiperclocks input hcsl *r3 33 *r4 33 clk nclk 2.5v 3.3v zo = 50 ? zo = 50 ? hiperclocks input r1 50 r2 50 *optional ? r3 and r4 can be 0 ? clk nclk hiperclocks input lvpecl 3.3v zo = 50 ? zo = 50 ? 3.3v r1 50 r2 50 r2 50 3.3v r1 100 lvds clk nclk 3.3v receiver zo = 50 ? zo = 50 ? clk nclk hiperclocks sstl 2.5v zo = 60 ? zo = 60 ? 2.5v 3.3v r1 120 r2 120 r3 120 r4 120
ICS85408I datasheet low skew, 1-to-8, differential-to-lvds clock distribution chip ics85408bgi revision b july 2, 2009 11 ?2009 integrated device technology, inc. 3.3v lvds driver termination a general lvds interface is shown in figure 3. in a 100 ? differential transmission line environment, lvds drivers require a matched load termination of 100 ? across near the receiver input. for a multiple lvds outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs. figure 3. typical lvds driver termination 3.3v lvds driver r1 100 ? ? + 3.3v 50 ? 50 ? 100 ? differential transmission line
ICS85408I datasheet low skew, 1-to-8, differential-to-lvds clock distribution chip ics85408bgi revision b july 2, 2009 12 ?2009 integrated device technology, inc. power considerations this section provides information on power dissipa tion and junction temperature for the ICS85408I. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ICS85408I is the sum of the co re power plus the analog power plus the power dissipated in t he load(s). the following is the power dissipation for v dd = 3.3v + 5% = 3.465v, which gives worst case results. power (core) max = v dd_max * i dd_max = 3.465v * 90ma = 311.85mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 70c/w per table 6 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.312w * 70c/w = 106.8c. this is well below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 6. thermal resistance ja for 24 lead tssop, forced convection ja by velocity meters per second 012.5 multi-layer pcb, jedec standard test boards 70c/w 65.0c/w 62c/w
ICS85408I datasheet low skew, 1-to-8, differential-to-lvds clock distribution chip ics85408bgi revision b july 2, 2009 13 ?2009 integrated device technology, inc. reliability information table 7. ja vs. air flow table for a 24 lead tssop transistor count the transistor count for ICS85408I is: 1821 pin compatible with sn65lvds104 package outline and package dimensions package outline - g suffix for 24 lead tssop table 8. package dimensions reference document: jedec publication 95, mo-153 ja by velocity meters per second 012.5 multi-layer pcb, jedec standard test boards 70c/w 65.0c/w 62c/w all dimensions in millimeters symbol minimum maximum n 16 a 1.20 a1 0.05 0.15 a2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 d 7.70 7.90 e 6.40 basic e1 4.30 4.50 e 0.65 basic l 0.45 0.75 0 8 aaa 0.10
ICS85408I datasheet low skew, 1-to-8, differential-to-lvds clock distribution chip ics85408bgi revision b july 2, 2009 14 ?2009 integrated device technology, inc. ordering information table 9. ordering information note: parts that are ordered with an "lf" suffix to the part number are the pb-free configuration and are rohs compliant. part/order number marking package shipping packaging temperature 85408bgi ics85408bgi 24 lead tssop tube -40 c to 85 c 85408bgit ics85408bgi 24 lead tssop 1000 tape & reel -40 c to 85 c 85408bgilf ics85408bgilf ?lead-free? 24 lead tssop tube -40 c to 85 c 85408bgilft ics85408bgilf ?lead-free? 24 lead tssop 1000 tape & reel -40 c to 85 c while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this produc t is intended for use in normal commercial and industrial applications. any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not aut horize or warrant any idt product for use in life support devices or critical medical instruments.
ICS85408I datasheet low skew, 1-to-8, differential-to-lvds clock distribution chip ics85408bgi revision b july 2, 2009 15 ?2009 integrated device technology, inc. revision history sheet rev table page description of change date a 1 pin assignment - corrected package information from 300-mil to 173-mil. 8/25/04 a t8 1 11 features section - added lead-free bullet. corrected block diagram. ordering information table - added lead-free information. 4/25/05 b t5 5 6 12 ac characteristics table - added additive phase jitter spec. added additive phase jitter plot. added power considerations section. converted datasheet format. 6/25/09
ICS85408I datasheet low skew, 1-to-8, differential-to-lvds clock distribution chip disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the ri ght to modify the products and/or specif ications described herein at any time and at idt? s sole discretion. all information in this document, including descriptions of product features and performance, is s ubject to change without notice. performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. the informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt?s products for any partic ular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in life support systems or similar devices where the failure or malfunction of an idt p roduct can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own ri sk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered tr ademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2009. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056

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